Project Start:
Project Finish: 		Tue 16/01/07
Sat 28/04/07


Tasks

ID
Task Name
DurationStartFinishResource Names% Complete
1
Video Generator
89 days?Tue 16/01/07Sat 28/04/07Hrishkesh[50%],Aparna[50%]0%
2
Phase I - Study
21 days?Tue 16/01/07Thu 08/02/07 0%
3
FPGA
8 days?Tue 16/01/07Wed 24/01/07 0%
4
What are FPGA's
2 daysTue 16/01/07Wed 17/01/07Hrishkesh,Aparna0%
5
How are FPGA's programmed
3 daysThu 18/01/07Sat 20/01/07Hrishkesh,Aparna0%
6
XESS/Digilent FPGA Boards
2 daysMon 22/01/07Tue 23/01/07Hrishkesh,Aparna0%
7
Documentation
1 day?Wed 24/01/07Wed 24/01/07 0%
8
Video Signals
7 days?Thu 25/01/07Thu 01/02/07 0%
9
What is video?
1 dayThu 25/01/07Thu 25/01/07Hrishkesh,Aparna0%
10
Raster Scanning
1 day?Fri 26/01/07Fri 26/01/07Hrishkesh,Aparna0%
11
Concepts of RGB Signals
2 days?Sat 27/01/07Mon 29/01/07Hrishkesh,Aparna0%
12
Importance of HS and VS
2 daysTue 30/01/07Wed 31/01/07Hrishkesh,Aparna0%
13
Documentation
1 day?Thu 01/02/07Thu 01/02/07 0%
14
Xilinx ISE Webpack
6 days?Fri 02/02/07Thu 08/02/07 0%
15
Get familiar with Xilinx Tools
1 day?Fri 02/02/07Fri 02/02/07Hrishkesh,Aparna0%
16
Understand the concepts of Synthesis
1 day?Sat 03/02/07Sat 03/02/07Hrishkesh,Aparna0%
17
Understand the concept of mapping
1 dayMon 05/02/07Mon 05/02/07Hrishkesh,Aparna0%
18
Dummy code download on the board
2 daysTue 06/02/07Wed 07/02/07Hrishkesh,Aparna0%
19
Documentation
1 day?Thu 08/02/07Thu 08/02/07 0%
20
Phase II - Generate RGB
10 days?Fri 09/02/07Tue 20/02/07 0%
21
Verilog Code to generate HS and VS
5 daysFri 09/02/07Wed 14/02/07Aparna0%
22
Testbench to test HS and VS
3 daysThu 15/02/07Sat 17/02/07Aparna0%
23
Verilog Code to generate RGB
5 daysFri 09/02/07Wed 14/02/07Hrishkesh0%
24
Testbench to test RGB generation
3 daysThu 15/02/07Sat 17/02/07Hrishkesh0%
25
Phase II Documentation
2 days?Mon 19/02/07Tue 20/02/07 0%
26
Phase III - Generate patterns
17 days?Wed 21/02/07Mon 12/03/07 0%
27
Verilog code to generate a circle
5 daysWed 21/02/07Mon 26/02/07Hrishkesh0%
28
Testbench to test the above
3 daysTue 27/02/07Thu 01/03/07Hrishkesh0%
29
Verilog code to generate Squar
5 daysWed 21/02/07Mon 26/02/07Aparna0%
30
Testbench
3 daysTue 27/02/07Thu 01/03/07Aparna0%
31
Generate pattern given the coordinates
7 daysFri 02/03/07Fri 09/03/07Hrishkesh0%
32
Testbench
7 daysFri 02/03/07Fri 09/03/07Aparna0%
33
Phase III Documentation
2 days?Sat 10/03/07Mon 12/03/07 0%
34
Phase IV
27 days?Tue 13/03/07Thu 12/04/07Hrishkesh,Aparna0%
35
Human Interface<TBD>
25 days?Tue 13/03/07Tue 10/04/07Hrishkesh,Aparna0%
36
Phase IV Documentation
2 days?Wed 11/04/07Thu 12/04/07 0%
37
Documentation
14 days?Fri 13/04/07Sat 28/04/07 0%
38
Final report
14 days?Fri 13/04/07Sat 28/04/07 0%

Resources

IDNameGroupMax UnitsPeak Units
1Hrishkesh 100%250%
2Aparna 100%250%

Assignments

Task IDTask NameResource NameWorkStartFinish% Work Complete
1Video GeneratorHrishkesh356 hrsTue 16/01/07Sat 28/04/070%
1Video GeneratorAparna356 hrsTue 16/01/07Sat 28/04/070%
4What are FPGA'sHrishkesh16 hrsTue 16/01/07Wed 17/01/070%
4What are FPGA'sAparna16 hrsTue 16/01/07Wed 17/01/070%
5How are FPGA's programmedHrishkesh24 hrsThu 18/01/07Sat 20/01/070%
5How are FPGA's programmedAparna24 hrsThu 18/01/07Sat 20/01/070%
6XESS/Digilent FPGA BoardsHrishkesh16 hrsMon 22/01/07Tue 23/01/070%
6XESS/Digilent FPGA BoardsAparna16 hrsMon 22/01/07Tue 23/01/070%
9What is video?Hrishkesh8 hrsThu 25/01/07Thu 25/01/070%
9What is video?Aparna8 hrsThu 25/01/07Thu 25/01/070%
10Raster ScanningHrishkesh8 hrsFri 26/01/07Fri 26/01/070%
10Raster ScanningAparna8 hrsFri 26/01/07Fri 26/01/070%
11Concepts of RGB SignalsHrishkesh16 hrsSat 27/01/07Mon 29/01/070%
11Concepts of RGB SignalsAparna16 hrsSat 27/01/07Mon 29/01/070%
12Importance of HS and VSHrishkesh16 hrsTue 30/01/07Wed 31/01/070%
12Importance of HS and VSAparna16 hrsTue 30/01/07Wed 31/01/070%
15Get familiar with Xilinx ToolsHrishkesh8 hrsFri 02/02/07Fri 02/02/070%
15Get familiar with Xilinx ToolsAparna8 hrsFri 02/02/07Fri 02/02/070%
16Understand the concepts of SynthesisHrishkesh8 hrsSat 03/02/07Sat 03/02/070%
16Understand the concepts of SynthesisAparna8 hrsSat 03/02/07Sat 03/02/070%
17Understand the concept of mappingHrishkesh8 hrsMon 05/02/07Mon 05/02/070%
17Understand the concept of mappingAparna8 hrsMon 05/02/07Mon 05/02/070%
18Dummy code download on the boardHrishkesh16 hrsTue 06/02/07Wed 07/02/070%
18Dummy code download on the boardAparna16 hrsTue 06/02/07Wed 07/02/070%
21Verilog Code to generate HS and VSAparna40 hrsFri 09/02/07Wed 14/02/070%
22Testbench to test HS and VSAparna24 hrsThu 15/02/07Sat 17/02/070%
23Verilog Code to generate RGBHrishkesh40 hrsFri 09/02/07Wed 14/02/070%
24Testbench to test RGB generationHrishkesh24 hrsThu 15/02/07Sat 17/02/070%
27Verilog code to generate a circleHrishkesh40 hrsWed 21/02/07Mon 26/02/070%
28Testbench to test the aboveHrishkesh24 hrsTue 27/02/07Thu 01/03/070%
29Verilog code to generate SquarAparna40 hrsWed 21/02/07Mon 26/02/070%
30TestbenchAparna24 hrsTue 27/02/07Thu 01/03/070%
31Generate pattern given the coordinatesHrishkesh56 hrsFri 02/03/07Fri 09/03/070%
32TestbenchAparna56 hrsFri 02/03/07Fri 09/03/070%
34Phase IVHrishkesh216 hrsTue 13/03/07Thu 12/04/070%
34Phase IVAparna216 hrsTue 13/03/07Thu 12/04/070%
35Human Interface<TBD>Hrishkesh200 hrsTue 13/03/07Tue 10/04/070%
35Human Interface<TBD>Aparna200 hrsTue 13/03/07Tue 10/04/070%


Microsoft Home Page
Microsoft Project Home Page